We present a VLSI CMOS-mixed analog-digital circuit for high-rate pixel X-ray imaging applications. It consists of 32 channels at 80 mu m pitch. The total die size is 3.7 x 14 mm(2). Each channel features: a low-noise charge preamplifier, a CR-RC shaper, a buffer, a threshold discriminator and a 16-bit binary counter. The readout is done serially on a tri-state buffer. The main parameters of the analog part are: shaping time of 850 ns at 5 pF input capacitance, gain of 180 mV/fC, ENC (e(-) rms) = 60 + 17 C-d (pF) and a power consumption of 3.8 W/channel. The counting rate is limited by the analog part to around 100 kHz/channel for 1 fC charge pulses. Due to the parallelism of the circuit, photon rate in the order of 1 GHz/cm(2) can be measured for a pixel size of the order of 200 x 200 mu m(2). The parameters of the circuit were optimised for the Syrmep experiment, an R&D project in digital mammography. The circuit was produced in 1.2 mu m CMOS technology by AMS (Austria). Characterisation of the circuit, as well as first-imaging results of the circuit connected to microstrips or pixel detectors are presented. They show the circuit works according to specification and can be used for imaging applications.

Castor 1.0, a VLSI analog-digital circuit for pixel imaging applications

PREST, MICHELA;
1997-01-01

Abstract

We present a VLSI CMOS-mixed analog-digital circuit for high-rate pixel X-ray imaging applications. It consists of 32 channels at 80 mu m pitch. The total die size is 3.7 x 14 mm(2). Each channel features: a low-noise charge preamplifier, a CR-RC shaper, a buffer, a threshold discriminator and a 16-bit binary counter. The readout is done serially on a tri-state buffer. The main parameters of the analog part are: shaping time of 850 ns at 5 pF input capacitance, gain of 180 mV/fC, ENC (e(-) rms) = 60 + 17 C-d (pF) and a power consumption of 3.8 W/channel. The counting rate is limited by the analog part to around 100 kHz/channel for 1 fC charge pulses. Due to the parallelism of the circuit, photon rate in the order of 1 GHz/cm(2) can be measured for a pixel size of the order of 200 x 200 mu m(2). The parameters of the circuit were optimised for the Syrmep experiment, an R&D project in digital mammography. The circuit was produced in 1.2 mu m CMOS technology by AMS (Austria). Characterisation of the circuit, as well as first-imaging results of the circuit connected to microstrips or pixel detectors are presented. They show the circuit works according to specification and can be used for imaging applications.
1997
SYRMEP; VLSI CMOS ASIC; X-ray imaging; silicon strip detector
Colledani, C; Comes, G; Dulinski, W; Hu, Y; Loddo, F; Turchetta, R; Bonvicini, V; Castelli, E; Pontoni, D; Prest, Michela; Rashevsky, A; Vacchi, A....espandi
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11383/1791095
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