We define a simple process calculus, based on Hennessy and Regan’s Timed Process Language, for specifying networks of communicating programmable logic controllers (PLCs) enriched with monitors enforcing specifications compliance. We define a synthesis algorithm that given an uncorrupted PLC returns a monitor that enforces the correctness of the PLC, even when injected with malware that may forge/drop actuator commands and inter-controller communications. Then, we strengthen the capabilities of our monitors by allowing the insertion of actions to mitigate malware activities. This gives us deadlock-freedom monitoring: malware may not drag monitored controllers into deadlock states.

A process calculus approach to correctness enforcement of PLCs

Lanotte R.;
2020-01-01

Abstract

We define a simple process calculus, based on Hennessy and Regan’s Timed Process Language, for specifying networks of communicating programmable logic controllers (PLCs) enriched with monitors enforcing specifications compliance. We define a synthesis algorithm that given an uncorrupted PLC returns a monitor that enforces the correctness of the PLC, even when injected with malware that may forge/drop actuator commands and inter-controller communications. Then, we strengthen the capabilities of our monitors by allowing the insertion of actions to mitigate malware activities. This gives us deadlock-freedom monitoring: malware may not drag monitored controllers into deadlock states.
2020
CEUR Workshop Proceedings
21st Italian Conference on Theoretical Computer Science, ICTCS 2020
ita
2020
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11383/2115144
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