Availability of streams of random numbers is critical in a number of significant applications. e.g. computer security and cryptography, privacy preservation procedures, IoT secure communication, numerical simulation of complex phenomena, gaming and gambling. Hardware generation of random numbers, especially when based on quantum phenomena, is made unbreakable by the same laws of nature. Random Power [1] [2] is focusing on the development of a Quantum-True Random Number generation (QTRNG) platform, producing unpredictable bit streams analyzing the time series of self-amplified endogenous pulses due to stochastically generated charge carriers in a dedicated silicon device. As per NIST recommendations [3], a SHA256 conditioning function was used in order to reduce potential biases and guarantee the required level of entropy. This paper reports the firmware development and implementation of a real-time SHA256 accelerator, which is capable of generating bits in bursts at a maximum rate of 330 Mbps.

A Method for Implementing a SHA256 Hardware Accelerator Inside an Quantum True Random Number Generator (QTRNG)

Witek K.;Caccia M.;Baszczyk M.;Dorosz P.;
2023-01-01

Abstract

Availability of streams of random numbers is critical in a number of significant applications. e.g. computer security and cryptography, privacy preservation procedures, IoT secure communication, numerical simulation of complex phenomena, gaming and gambling. Hardware generation of random numbers, especially when based on quantum phenomena, is made unbreakable by the same laws of nature. Random Power [1] [2] is focusing on the development of a Quantum-True Random Number generation (QTRNG) platform, producing unpredictable bit streams analyzing the time series of self-amplified endogenous pulses due to stochastically generated charge carriers in a dedicated silicon device. As per NIST recommendations [3], a SHA256 conditioning function was used in order to reduce potential biases and guarantee the required level of entropy. This paper reports the firmware development and implementation of a real-time SHA256 accelerator, which is capable of generating bits in bursts at a maximum rate of 330 Mbps.
2023
AA.VV.
Mixed Design of Integrated Circuits and System, MIXDES 2023
9788363578244
30th International Conference on Mixed Design of Integrated Circuits and System, MIXDES 2023
Krakow
9 June 2022 through 30 June 2022
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11383/2187440
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